At first glance, programming an SDRAM controller can seem like a formidable task. Indeed, numerous Synchronous Dynamic Random Access Memory (DRAM) technologies have been developed. In a never-ending quest for performance and density, many different architectures and modes of operation have been developed.
We examine the AMCC PowerPC 405GP processor for this discussion of SDRAM interface considerations. You might want to have a copy of the user manual to reference while we explore the issues related to SDRAM interfacing. This document is referenced in Section D.4.1, "Suggestions for Additional Reading."
To understand SDRAM setup, it is necessary to understand the basics of how an SDRAM device operates. Without going into the details of the hardware design, an SDRAM device is organized as a matrix of cells, with a number of address bits dedicated to row addressing and a number dedicated to column addressing. Figure D-1 illustrates this.
Figure D-1. Simplified SDRAM block diagram
Inside the memory matrix, the circuitry is quite complex. A simplified example of a read operation is as follows: A given memory location is referenced by placing a row address on the row address lines and then placing a column address on the column address lines. After some time has passed, the data stored at the location addressed by the row and column inputs are made available to the processor on the data bus.
The processor outputs a row address on the SDRAM address bus and asserts its Row Address Select (RAS) signal. After a short preprogrammed delay to allow the SDRAM circuitry to capture the row address, the processor outputs a column address and asserts its Column Address Select (CAS) signal. The SDRAM controller translates the actual physical memory address into row and column addresses. Many SDRAM controllers can be configured with the row and column width sizes; the PPC405GP is one of those examples. Later you will see that this must be configured as part of the SDRAM controller setup.
This example is much simplified, but the concepts are the same. A burst read, for example, which reads four memory locations at once, outputs a single RAS and CAS cycle, and the internal SDRAM circuitry automatically increments the column address for the subsequent three locations of the burst read, eliminating the need for the processor to issue four separate CAS cycles. This is but one example of performance optimization. The best way to understand this is to absorb the details of an actual memory chip. An example of a well-written data sheet is included in Section D.4.1, "Suggestions for Additional Reading."
An SDRAM is composed of a single transistor and a capacitor. The transistor supplies the charge, and the capacitor's job is to retain (store) the value of the individual cell. For reasons beyond the scope of this discussion, the capacitor can hold the value for only a small duration. One of the fundamental concepts of dynamic memory is that the capacitors representing each cell must be periodically recharged to maintain their value. This is referred to as SDRAM refresh.
A refresh cycle is a special memory cycle that neither reads nor writes data to the memory. It simply performs the required refresh cycle. One of the primary responsibilities of an SDRAM controller is to guarantee that refresh cycles are issued in time to meet the chip's requirements.
The chip manufacturers specify minimum refresh intervals, and it is the designer's job to guarantee it. Usually the SDRAM controller can be configured directly to select the refresh interval. The PowerPC 405GP presented here has a register specifically for this purpose. We will see this shortly.
The term synchronous implies that the data read and write cycles of an SDRAM device coincide with the clock signal from the CPU. SDR SDRAM is read and written on each SDRAM clock cycle. DDR SDRAM is read and written twice on each clock cycle, once on the rising edge of the clock and once on the falling edge.
Modern processors have complex clocking subsystems. Many have multiple clock rates that are used for different parts of the system. A typical processor uses a relatively low-frequency crystal-generated clock source for its primary clock signal. A phase locked loop internal to the processor generates the CPU's primary clock (the clock rate we speak of when comparing processor speeds). Because the CPU typically runs much faster than the memory subsystem, the processor generates a submultiple of the main CPU clock to feed to the SDRAM subsystem. You need to configure this clocking ratio for your particular CPU and SDRAM combination.
The processor and memory subsystem clocks must be correctly configured for your SDRAM to work properly. Your processor manual contains a section on clock setup and management, and you must consult this to properly set up your particular board design.
The AMCC 405GP is typical of processors of its feature set. It takes a single crystal-generated clock input source and generates several internal and external clocks required of its subsystems. It generates clocks for the CPU, PCI interface, Onboard Peripheral Bus (OPB), Processor Local Bus (PLB), Memory Clock (MemClk), and several internal clocks for peripherals such as timer and UART blocks. A typical configuration might look like those in Table D-1.
Table D-1. Typical PPC405GP Clock Configuration
| Clock | Rate | Comments |
|---|---|---|
| Crystal reference | 33MHz | Fundamental reference supplied to processor |
| CPU clock | 133MHz | Derived from processor's internal PLL, controlled by hardware pin strapping and register settings. |
| PLB clock | 66MHz | Derived from CPU clock and configured via hardware pin strapping and register settings. Used for internal processor local bus data interchange among its high-speed modules. |
| OPB clock | 66MHz | Derived from PLB clock and configured via register settings. Used for internal connection of peripherals that do not need high-speed connection. |
| PCI clock | 33MHz | Derived from PLB clock and configured via register settings. |
| MemClk | 100MHz | Drives the SDRAM chips directly. Derived from CPU clock and configured via register settings. |
Decisions about clock setup normally must be made at hardware design time. Pin strapping options determine initial clock configurations upon application of power to the processor. Some control over derived clocks is often available by setting divider bits accessible through processor internal registers dedicated to clock and subsystem control. In the example we present here based on the 405GP, final clock configuration is determined by pin strapping and firmware configuration. It is the bootloader's responsibility to set the initial dividers and any other clock options configurable via processor register bits very early after power is applied.
After the clocks have been configured, the next step is to configure the SDRAM controller. Controllers vary widely from processor to processor, but the end result is always the same: You must provide the correct clocking and timing values to enable and optimize the performance of the SDRAM subsystem.
As with other material in this book, there is no substitute for detailed knowledge of the hardware you are trying to configure. This is especially so for SDRAM. It is beyond the scope of this appendix to explore the design of SDRAM, but some basics must be understood. Many manufacturers' data sheets on SDRAM devices contain helpful technical descriptions. You are urged to familiarize yourself with the content of these data sheets. You don't need a degree in hardware engineering to understand what must be done to properly configure your SDRAM subsystem, but you need to invest in some level of understanding.
Here we examine how the SDRAM controller is configured on the 405GP processor as configured by the U-Boot bootloader we covered in Chapter 7, "Bootloaders." Recall from Chapter 7 that U-Boot provides a hook for SDRAM initialization from the assembly language startup code found in start.S in the 4xx-specific cpu directory. Refer back to Section 7.4.4 "Board-Specific Initialization" in Chapter 7. Listing D-1 reproduces the sdram_init() function from U-Boot's .../cpu/ppc4xx/sdram.c file.
Listing D. ppc4xx sdram_init() from U-Boot
01 void sdram_init(void)
02 {
03 ulong sdtr1;
04 ulong rtr;
05 int i;
06
07 /*
08 * Support for 100MHz and 133MHz SDRAM
09 */
10 if (get_bus_freq(0) > 100000000) {
11 /*
12 * 133 MHz SDRAM
13 */
14 sdtr1 = 0x01074015;
15 rtr = 0x07f00000;
16 } else {
17 /*
18 * default: 100 MHz SDRAM
19 */
20 sdtr1 = 0x0086400d;
21 rtr = 0x05f00000;
22 }
23
24 for (i=0; i<N_MB0CF; i++) {
25 /*
26 * Disable memory controller.
27 */
28 mtsdram0(mem_mcopt1, 0x00000000);
29
30 /*
31 * Set MB0CF for bank 0.
32 */
33 mtsdram0(mem_mb0cf, mb0cf[i].reg);
34 mtsdram0(mem_sdtr1, sdtr1);
35 mtsdram0(mem_rtr, rtr);
36
37 udelay(200);
38
39 /*
40 * Set memory controller options reg, MCOPT1.
41 * Set DC_EN to '1' and BRD_PRF to '01' for 16 byte PLB Burst
42 * read/prefetch.
43 */
44 mtsdram0(mem_mcopt1, 0x80800000);
45
46 udelay(10000);
47
48 if (get_ram_size(0, mb0cf[i].size) == mb0cf[i].size) {
49 /*
50 * OK, size detected -> all done
51 */
52 return;
53 }
54 }
55}
The first action reads the pin strapping on the 405GP processor to determine the design value for the SDRAM clock. In this case, we can see that two possible values are accommodated: 100MHz and 133MHz. Based on this choice, constants are chosen that will be used later in the function to set the appropriate register bits in the SDRAM controller.
Starting on line 24, a loop is used to set the parameters for each of up to five predefined memory sizes. Currently, U-Boot has logic to support a single bank of memory sized at 4MB, 16MB, 32MB, 64MB, or 128MB. These sizes are defined in a table called mb0cf in .../cpu/ppc4xx/sdram.c. The table associates a constant with each of these memory sizes, based on the value required in the 405GP memory bank configuration register. The loop does this:
for (i = each possible memory bank size, largest first) {
select timing constant based on SDRAM clock speed;
disable SDRAM memory controller;
configure bank 0 with size[i], timing constants[i];
re-enable SDRAM memory controller;
run simple memory test to dynamically determine size;
/* This is done using get_ram_size() */
if (tested size == configured size) done;
}
This simple logic simply plugs in the correct timing constants in the SDRAM controller based on SDRAM clock speed and configured memory bank size from the hard-coded table in U-Boot. Using this explanation, you can easily correlate the bank configuration values using the 405GP reference manual. For a 64MB DRAM size, the memory bank control register is set as follows:
Memory Bank 0 Control Register = 0x000a4001
The PowerPC 405GP User's Manual describes the fields in Table D-2 for the memory bank 0 control register.
Table D-2. 405GP Memory Bank 0-3 Configuration Register Fields
| Field | Value | Comments |
|---|---|---|
| Bank Address (BA) | 0x00 | Starting memory address of this bank. |
| Size (SZ) | 0x4 | Size of this memory bankin this case, 64MB. |
| Addressing Mode (AM) | 0x2 | Determines the organization of memory, including the number of row and column bits. In this case, Mode 2 = 12 row address bits, and either 9 or 10 column address bits, and up to four internal SDRAM banks. This data is provided in a table in the 405GP user's manual. |
| Bank Enable (BE) | 0x1 | Enable bit for the bank configured by this register. There are four of these memory bank configuration registers in the 405GP. |
The values in this table must be determined by the designer, based on the choice of memory module in use on the board.
Let's look at a timing example for more detail on the timing requirements of a typical SDRAM controller. Assuming a 100MHz SDRAM clock speed and 64MB memory size, the timing constants selected by the sdram_init() function in Listing D-1 are selected as follows:
SDRAM Timing Register = 0x0086400d
Refresh Timing Register = 0x05f00000
The PowerPC 405GP User's Manual describes the fields in Table D-3 for the SDRAM Timing Register.
Table D-3. 405GP SDRAM Timing Register Fields
| Field | Value | Comments |
|---|---|---|
| CAS Latency (CASL) | 0x1 | SDRAM CAS Latency. This value comes directly from the SDRAM chip specifications. It is the delay in clock cycles required by the chip between issuance of the read command (CAS signal) until the data is available on the data bus. In this case, the 0x1 represents two clock cycles, as seen from the 405GP user's manual. |
| Precharge Command to Next Activate (PTA) | 0x1 | The SDRAM Precharge command deactivates a given row. In contrast, the Activate command enables a given row for subsequent access, such as during a burst cycle. This timing parameter enforces the minimum time between Precharge to a subsequent Activate cycle and is dictated by the SDRAM chip. The correct value must be obtained from the SDRAM chip specification. In this case, 0x1 represents two clock cycles, as determined from the 405GP user's manual. |
| Read/Write to Precharge Command Minimum (CTP) | 0x2 | This timing parameter enforces the minimum time delay between a given SDRAM read or write command to a subsequent Precharge command. The correct value must be obtained from the SDRAM chip specification. In this case, 0x2 represents three clock cycles, as determined from the 405GP user's manual. |
| SDRAM Command Leadoff (LDF) | 0x1 | This timing parameter enforces the minimum time delay between assertion of address or command cycle to bank select cycle. The correct value must be obtained from the SDRAM chip specification. In this case, 0x1 represents two clock cycles, as determined from the 405GP user's manual. |
The final timing parameter configured by the U-Boot example in Listing D-1 is the refresh timing register value. This register requires a single field that determines the refresh interval enforced by the SDRAM controller. The field representing the interval is treated as a simple counter running at the SDRAM clock frequency. In the example here, we assumed 100MHz as the SDRAM clock frequency. The value programmed into this register in our example is 0x05f0_0000. From the PowerPC 405GP User's Manual, we determine that this will produce a refresh request every 15.2 microseconds. As with the other timing parameters, this value is dictated by the SDRAM chip specifications.
A typical SDRAM chip requires one refresh cycle for each row. Each row must be refreshed in the minimum time specified by the manufacturer. In the chip referenced in Section D.4.1, "Suggestions for Additional Reading," the manufacturer specifies that 8,192 rows must be refreshed every 64 milliseconds. This requires generating a refresh cycle every 7.8 microseconds to meet the specifications for this particular device.
SDRAM devices are quite complex. This appendix presented a very simple example to help you navigate the complexities of SDRAM controller setup. The SDRAM controllers perform a critical function and must be properly set up. There is no substitute to diving into a specification and digesting the information presented. The two example documents referenced in this appendix are excellent starting points.
AMCC 405GP Embedded Processor User's Manual
AMCC Corporation
www.amcc.com/Embedded/
Micron Technology, Inc.
Synchronous DRAM MT48LC64M4A2 Data Sheet
http://download.micron.com/pdf/datasheets/dram/sdram/256MSDRAM.pdf